Patent · US Active

Security plugin for a system-on-a-chip platform

US11263352B2 · kind B2 · utility

2Cited by

32References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Manoj Sastry · Portland, US
Alpa T. Narendra Trivedi · Hillsboro, US
Men Long · Hillsboro, US

Key dates

Filing date	Jul 23, 2020
Grant date	Mar 1, 2022
Priority date	—
Expiry date	Aug 21, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/76
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.