Failsafe circuit, layout, device, and method
US11263380B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 31, 2018 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Apr 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.