Duo-level word line driver
US11264093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.