Method and apparatus for determining expansion compensation in photoetching process, and method for manufacturing device
US11264242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Mar 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.