Semiconductor fabrication method for producing nano-scaled electrically conductive lines
US11264271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Oct 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.