Antifuse memory arrays with antifuse elements at the back-end-of-line (BEOL)

US11264317B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Vincent Dorgan · Hillsboro, US
• Jeffrey Hicks · Manning, US
• Miriam Reshotko · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Ilan Tsameret · Portland, US

Key dates

• Filing date: Apr 2, 2018
• Grant date: Mar 1, 2022
• Expiry date: Jun 30, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.