Transistors with reduced defect and methods forming same
US11264478B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Oct 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.