Soft FEC with parity check
US11265109B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Mar 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0096
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.