Key exchange schemes with addressable elements
US11265151B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Jul 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.