High-throughput multi-node integrated circuits
US11265268B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The technology described in this document can be embodied in an integrated circuit device comprises a first data processing unit comprising one or more input ports for receiving incoming data, one or more inter-unit data links that couple the first data processing unit to one or more other data processing units, a first ingress management module connected to the one or more inter-unit data links, the first ingress management module configured to store the incoming data, and forward the stored data to the one or more inter-unit data links as multiple data packets, and a first ingress processing module. The integrated circuit device also comprises a second data processing unit comprising one or more output ports for transmitting outgoing data, and a second ingress management module connected to the one or more inter-unit data links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.