Multi sleep mode power saving
US11269398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reducing power consumption of an electrical device is provided. The electrical device includes a first and a second module. The first and second modules include a first and a second memory, and a first and second system on chip (SoC) respectively. The first and second SoCs include a first and a second micro-processor respectively. A PCI-e bus connects the modules. The second module enters a sleep mode state that includes a first and a second sleep mode. The second module transitions between the first and second sleep modes while in the sleep mode state. The second SoC reduces a power state of the second module during the first sleep mode, and powers off the second SoC during the second sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.