Map reduce using coordination namespace hardware acceleration
US11269687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2019 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/2255
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for supporting data MapReduce operations in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing and communicating data generated by local processes running at the nodes, and coordinated to provide MapReduce operations in a multi-nodal system. A hardware accelerated mechanism supports map reduce sorting/shuffle operations and reduce operations according to an aggregate function. Local processes running at a node generate a tuple corresponding to data generated by a process, each tuple having a tuple name and tuple data value corresponding to the generated data. Each tuple is processed and stored at the node or another node, dependent upon its tuple name. Tuple records associated with a tuple name are accumulated at one or more nodes according to a linked list structure at each that is accessible via a hash table index pointer at the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.