Memory controller and memory system including the same
US11269723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Aug 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.