Managing memory in an electronic device
US11269788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Aug 18, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.