Two-bit memory cell and circuit structure calculated in memory thereof
US11270764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2021 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.