Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device
US11270885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jun 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.