Method for forming a via hole self-aligned with a metal block on a substrate

US11270912B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Martin O'Toole · Dresden, DE
• Christopher Wilson · Tervuren, BE
• Zsolt Tokei · Leuven, BE
• Ryan Ryoung-Han Kim · Albany, US

Key dates

• Filing date: Dec 3, 2020
• Grant date: Mar 8, 2022
• Expiry date: Dec 3, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.