Method of manufacturing power semiconductor device and power semiconductor device
US11270982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jan 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal mask is disposed on a copper base plate. A solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste on each of copper plates of the copper base plate. A semiconductor element and a conductive component are placed on the respective patterns of the solder pastes. A metal mask is disposed on the copper base plate. Then, a solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste covering each of the semiconductor element and the conductive component. A large-capacity relay board is disposed so as to come into contact with a corresponding pattern of the solder paste. A power semiconductor device is completed by performing heat treatment under a temperature condition of 200° C. or higher.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.