Array substrate and fabrication method thereof, display apparatus
US11271016B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Oct 10, 2017 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Dec 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array substrate is disclosed. The array substrate may include a base substrate, gate lines and data lines intersecting the gate lines on the base substrate. The gate lines and the data lines may define a plurality of pixel regions. Each of at least some of the plurality of the pixel regions may be provided with an image sensor. The image sensor may include a sensitive element, a first electrode at one end of the sensitive element, and a second electrode at the other end of the sensitive element. The image sensor may be configured to sense light having image information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.