Medium voltage planar DC bus distributed capacitor array
US11271492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jul 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.