Synchronous divider based on cascaded retiming
US11271550B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Apr 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.