Frequency divider circuit, communication circuit, and integrated circuit
US11271568B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Dec 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.