Daisy-chained synchronous ethernet clock recovery
US11271712B2 · kind B2 · utility
1Cited by
11References
16Claims
0Family size
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Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Apr 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.