Apparatus, system, and method for an integrated circuit
US11275109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2018 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Manufacturing integrated circuits is discussed with steps as follows. Creating a wafer with a plurality of dies, where each die contains its own integrated circuit. Fabricating multiple instances of TAP circuitry located in a margin between dies of the wafer. Fabricating on the wafer one row of test pads and power pads per group of dies on the wafer, where the row of test pads and power pads is electrically connected and shared among all of the dies in the group. The test and power pads connect to a chain of TAP circuitry in order to supply operating power as well as testing data to verify the integrity of each die in that group of dies. Singulating the dies to create each instance of the integrated circuit, and during the singulation process, the TAP circuitry located in the margin between the dies is destroyed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.