Tamper monitoring circuitry
US11275401B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Sep 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.