Patent · US Active

Circuitry for low-precision deep learning

US11275998B2 · kind B2 · utility

1Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Martin Langhammer · Calne, GB
Sudarshan Srinivasan · Savanuru, IN
Gregg William Baeckler · San Jose, US
Duncan Moss · Hillsboro, US
Sasikanth Avancha · Bengaluru, IN
Dipankar Das · Pune, IN

Key dates

Filing date	May 31, 2018
Grant date	Mar 15, 2022
Priority date	—
Expiry date	Jul 7, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03M7/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.