Reconfigurable image processing hardware pipeline
US11276134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Apr 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.