Semiconductor structure and forming method thereof
US11276608B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5329
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a forming method thereof are provided. The forming method includes: providing a base, where a mask material layer is formed on the base, a plurality of first trenches disposed at intervals are formed in the mask material layer, an extension direction of the first trenches is a first direction, the plurality of first trenches are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a first side wall covering layer and a barrier layer, where the first side wall covering layer is located on a side wall of the first trench, the barrier layer is located in at least one of the first trenches, the barrier layer divides the first trench in the first direction, and the first side wall covering layer exposes side walls of the barrier layer on two sides in the first direction; forming a second side wall covering layer on the side walls of the barrier layer exposed by the first side wall covering layer; and etching the mask material layer between the adjacent first trenches by using the first side wall covering layer, the second side wall covering layer and the barrier layer as a mask to form a se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.