Back end of line via to metal line margin improvement
US11276638B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 7, 2019 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Jan 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a first conductive line and a second conductive line in a first dielectric layer, and a third conductive line in a second dielectric layer overlying the first dielectric layer. The first conductive line and the second conductive line each extend along a first direction. The third conductive line extends along a second direction different from the first direction and above at least the second conductive line. The semiconductor structure further includes a via in the second dielectric layer and electrically connecting the second conductive line and the third conductive line. The via lands on a portion of the second conductive line. The semiconductor structure further includes a dielectric cap over the first conductive line. A bottom surface of the dielectric cap is below a top surface of the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.