Semiconductor device
US11276768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2019 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Jan 16, 2039 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device including a structure having N gate electrode layers G and (N−1) channel formation region layers CH (where N≥3) alternately juxtaposed on an insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the nth channel formation region layer is connected to a fourth surface of the nth gate electrode layer. A fourth surface of the nth channel formation region layer is connected to a second surface of the (n+1)th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.