Semiconductor device and manufacturing method
US11276989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2018 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Jan 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/2068
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure is related to a semiconductor device and a method of manufacturing the said semiconductor device. The semiconductor device comprising a stacked configuration of a plurality of semiconductor layers. At least one of the semiconductor layers is a III-V compound semiconductor layer, and at least one of the III-V compound semiconductor layers has formed thereonto a corresponding crystalline terminating oxide layer, wherein the at least one of the plurality of semiconductor layers interfaces via its crystalline terminating oxide layer to a neighbouring epitaxial semiconductor layer thereto. The semiconductor device is a quantum well device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.