Photonics systems to enable top-side wafer-level optical and electrical test

US11280959B2 · kind B2 · utility

Assignee

• Ayar Labs, Inc. · US

Inventors

• Roy Meade · Boise, US
• Chen Sun · Berkeley, US
• Shahab Ardalan · Emeryville, US
• John Fini · Metuchen, US
• Forrest Sedgwick · Berkeley, US

Key dates

• Filing date: Apr 23, 2020
• Grant date: Mar 22, 2022
• Expiry date: Apr 23, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/34
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.