Processing system, related integrated circuit and method
US11281807B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0894
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.