Systems and methods for temperature-based parasitic capacitance variation compensation
US11282458B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Jun 9, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jun 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/041
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are presently disclosed that compensate for temperature-based parasitic capacitance variation of a pixel of a display by causing a driver transistor of the pixel to enter an ohmic or linear region. A lookup table is generated based on temperatures at the pixel, diode voltages, and target diode currents or luminances at a diode of the pixel. A correction voltage is determined based on a target diode current or luminance, a temperature at the pixel, and the lookup table. A data voltage is applied corresponding to the target diode current or luminance and the correction voltage to the driver transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.