Method of manufacturing semiconductor device including spacer
US11282841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.