Capping layers in metal gates of transistors
US11282938B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.