Device structure for increasing coupling ratio of body-tied fin structure flash memory cell
US11282968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jul 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
The present disclosure provides a device structure for increasing the coupling ratio of a body-tied fin flash memory cell. The device includes a plurality of elongate fin structures arranged in parallel in an active layer on a substrate, a floating gate disposed on the top surface and the opposing sidewalls of each of the fin structures and at a predetermined location on the elongated fin, and dispersed structure. The dispersed structure comprises a plurality of stacked layers parallel to the substrate, spaced evenly apart; and two adjacent fin structures share one dispersed structure at their sidewalls. This device increases the distance between adjacent floating gates, reduces coupling capacitance, and reduces the disturbance between the cells, which is conducive to increasing the drain voltage, improving the programming speed, and further reducing the gate voltage. More optimization options for subsequent shrinking of the flash memory cells can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.