Techniques to improve current regulator capability to protect the secured circuit from power side channel attack
US11283349B2 · kind B2 · utility
6Cited by
20References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Aug 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/305
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.