Synthesized clock synchronization between network devices
US11283454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jul 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.