Patent · US Active

Network-on-chip element placement

US11283729B2 · kind B2 · utility

0Cited by

10References

26Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Anup Gangwar · Bengaluru, IN
Nitin Agarwal · Bengaluru, IN
Honnahuggi Harinath Venkata Naga Ambica Prasad · Bengaluru, IN
Narayana Sri Harsha Gade · Bengaluru, IN
Ravishankar Sreedharan · Bengaluru, IN

Key dates

Filing date	Nov 10, 2020
Grant date	Mar 22, 2022
Priority date	—
Expiry date	Nov 10, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH04L49/109
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.