Digital pixel having high sensitivity and dynamic range
US11284025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jun 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/772
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.