Systems and methods for applying checkpoints on a secondary computer in parallel with transmission
US11288123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Jun 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a method of checkpointing. The method may include determining, by the primary computer, when to initiate a checkpoint point operation; dividing, at the primary computer, checkpoint data into two or more groups, wherein each group includes one or more pages of memory; transmitting a first group to the secondary computer; upon receiving, by the secondary computer, the first group, correlating memory pages in the first group with pages in memory on the secondary computer; determining, at the secondary computer, which bytes of memory pages of the first group differ from the correlated pages stored in memory in the secondary computer; and applying data from the first group by swapping differences between the memory pages of the first group and the correlated memory pages stored in the secondary computer. Where at least some of these multiple operations are performed in parallel during a subset of the overall checkpoint operation. The simultaneous performance of various memory manage checkpoint operations is advantageous in various fault tolerant systems. The differences may be N-byte differences such as 8-byte differences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.