Logical and physical address field size reduction by alignment-constrained writing technique
US11288204B2 · kind B2 · utility
1Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Dec 4, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.