Patent · US Active

Graph processing optimization method based on multi-FPGA accelerator interconnection

US11288221B2 · kind B2 · utility

1Cited by

2References

7Claims

0Family size

Assignee

Huazhong University of Science and Technology · CN

Inventors

Xiaofei Liao · Hubei, CN
Fan Zhang · Lake Barrington, US
Long Zheng · Shanghai, CN
Hai Jin · Hubei, CN
Zhiyuan Shao · Hubei, CN

Key dates

Filing date	Jun 9, 2020
Grant date	Mar 29, 2022
Priority date	—
Expiry date	Sep 14, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2209/509
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.