Gate-driving unit circuit having pre-pull down sub-circuit, gate driver on array circuit, driving method, and display apparatus thereof
US11289039B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a gate-driving unit circuit. The gate-driving unit circuit includes an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge a pull-up node to a turn-on voltage level. Additionally, the gate-driving unit circuit includes a pre-pull-down sub-circuit coupled to a pull-down node, a pre-pull-down node, and a reference voltage terminal, and configured to pull down voltage levels at the pull-down node and the pre-pull-down node to a turn-off voltage level before the pull-up node is charged to the turn-on voltage level. Therefore, potential charging delay in the pull-down node caused by a transistor threshold voltage shift is avoided. The gate-driving unit circuit further includes a pull-down sub-circuit, a pull-down control sub-circuit, a noise-reduction sub-circuit, a reset sub-circuit, and an output sub-circuit to couple with the input sub-circuit and the pre-pull-down sub-circuit to output a gate-driving signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.