Memory device and method for writing data
US11289159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | May 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.