Analog content addressable memory utilizing three terminal memory devices
US11289162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.