Electronic chip package
US11289391B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.