Integrated circuit with electrostatic discharge protection
US11289472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Jul 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/814
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.