Frequency synthesizer
US11290118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Dec 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.